1. Field of the Invention
The present invention relates to a technique of supporting verification of specifications for a design subject, such as software and hardware.
2. Description of the Related Art
Recently in the development of software and hardware, the scale of software and hardware as design subjects has been getting larger due to the progress of design technologies. Meanwhile, the ratio of a verification process with respect to the entire development process tends to be increasing. In the verification process, whether a design subject operates according to specifications is verified using a scenario created by a designer.
A specification of the design subject may be changed because of a discovered bug, a user request, etc. Such a case brings a need of recreating a test scenario in line with the specification change and re-verifying the design subject. However, if re-verification is performed on all test items every time a specification is changed, labor costs required for a regression test become enormous.
To improve work efficiency in a regression test conducted in the wake of a specification change, conventional techniques of selecting and executing a test scenario with a higher priority order have been provided.
However, according to the conventional techniques described in Japanese Patent Application Laid-Open Publication Nos. 2002-014847, H11-39363, and 2006-252489, the priority order of test scenarios given to a subject to be verified is not calculated in line with a specification change bringing about a problem of difficulty in identifying an area that is affected indirectly by the specification change. As a result, labor costs required for a regression test still increase, leading to a problem of a prolonged design period.